The present invention relates to copper (Cu) or Cu alloy metallization in semiconductor devices. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures.
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ultra large scale integration technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, typically doped monocrystalline silicon on which transistors are formed, and a plurality of sequentially formed inter-layer dielectrics (ILDs) and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trench openings typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor integrated circuits comprising five or more levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
A conductive plug filling a via hole is typically formed by depositing an ILD on a conductive layer comprising at least one conductive pattern, forming an opening through the ILD by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the ILD is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of all opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The transmission speed of a signal along an interconnection pattern varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the interconnection pattern limits the speed of the integrated circuit.
If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules, the rejection rate of ICs due to integrated circuit speed delays significantly reduces yield and increases manufacturing costs.
One way to increase the speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, patterning by photolithography and etching, or by damascene techniques wherein trenches are patterned and etched in dielectric layers and filled with a conductive material. Excess conductive material on the surface of the dielectric layer is then removed by CMP. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the sub-micron range, step coverage problems have arisen involving the use of Al which has decreased the reliability of interconnections formed between different wiring layers. Such poor step coverage results in high current density and enhanced electromigration. Moreover, low dielectric constant polyimide materials, when employed as interlayer dielectrics, create moisture/bias reliability problems when in contact with Al.
One approach to improved interconnection paths in vias comprises the use of completely filled plugs of a metal, such as of W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for a wiring metal and W plugs for interconnections at different levels. However, the use of W is attendant with several disadvantages. For example, most W processes are complex and expensive. Moreover, W has a high resistivity. The Joule heating may enhance electromigration of adjacent Al wiring. Furthermore, W plugs are susceptible to void formation, and the interface with the wiring layer usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem comprises the use of chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures for Al deposition. The use of CVD for depositing Al has proven expensive, while hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Cu and Cu alloys have received considerable attention as a candidate for replacing Al in VLSI interconnect metallizations. Cu exhibits superior electromigration properties and has a lower resistivity than Al. In addition, Cu has improved electrical properties vis-à-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring.
Electroless plating and electroplating of Cu and Cu alloys offer the prospect of low cost, high throughput, high quality plated films and efficient via, contact and trench filling capabilities. Electroless plating generally involves the controlled autocatalytic deposition of a continuous film on the catalytic surface by the interaction in solution of a metal salt and a chemical reducing agent. Electroplating comprises the electro deposition of an adherent metallic coating on an electrode employing externally supplied electrons to reduce metal ions in the plating solution. A seed layer is required to catalyze electroless deposition or to carry electrical current for electroplating. For electroplating, the seed layer must be continuous. For electroless plating, very thin catalytic layers, e.g., less than 100A, can be employed in the form of islets of catalytic metal.
There are disadvantages attendant upon the use of Cu or Cu alloys. For example, Cu readily diffuses through silicon dioxide, the typical dielectric interlayer material employed in the manufacture of semiconductor devices, into silicon elements and adversely affects device performance.
One approach to forming Cu plugs and wiring comprises the use of damascene structures employing CMP, as in Teong, U.S. Pat. No. 5,693,563. However, due to Cu diffusion through dielectric interlayer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten (W), tungsten nitride (WN), Ti-TiN, titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride (silicon nitride) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
There are, however, significant problems attendant upon conventional Cu interconnect methodology. For example, conventional practices comprise forming damascene openings in an ILD, depositing Cu or a Cu alloy layer, chemical-mechanical polishing, and forming a capping layer on the exposed surface of the Cu or Cu alloy. It was found, however, that after CMP, the exposed surface of the Cu or Cu alloy rapidly oxidizes resulting in the formation of a thin, porous and brittle copper oxide surface layer. Consequently, the capping layer exhibits poor adhesion to the Cu or Cu alloy surface and is vulnerable to removal, as by peeling due to scratching or stresses resulting from subsequent deposition of layers. As a result, the Cu or Cu alloy is not entirely encapsulated and Cu diffusion occurs thereby adversely affecting device performance and decreasing the electromigration resistance of the Cu or Cu alloy interconnect member.
As design rules extend deeper into the submicron range, e.g., about 0.18 microns and under, the reliability of the interconnect pattern becomes particularly critical. Accordingly, the adhesion of capping layers to Cu interconnects requires even greater reliability.
There exists a need for efficient methodology enabling the formation of encapsulated Cu and Cu alloy interconnect members having high reliability. There exists a particular need for selectively controlling the formation of a passivating layer on the exposed surface of the Cu or Cu alloy to improve process flow, device characteristics, and uniformity of device characteristics.
An advantage of the present invention is a method of manufacturing a semiconductor device having highly reliable Cu and Cu alloy interconnect members with substantially uniform characteristics.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising a Cu or Cu alloy interconnect member utilizing a selectively formed passivating layer.
Additional advantages of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor on a wafer, which method comprises:
forming a copper (Cu) or Cu alloy interconnection pattern comprising a dense array of spaced apart Cu or Cu alloy lines bordering an open dielectric field on a surface of the wafer; and
forming a passivating layer on the surface of the Cu or Cu alloy layer by:
(a) treating the surface of the Cu or Cu alloy layer with a solution of a copper corrosion-inhibiting compound; or
(b) electroless plating a metal layer on the surface of the Cu or Cu alloy layer; or
(c) depositing a metallic compound on the surface of the Cu/Cu alloy layer by chemical vapor deposition (CVD).
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described simply by way of illustrating of the best mode contemplated in carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
As used throughout this application, the symbol xe2x80x9cCuxe2x80x9d denotes elemental or substantially elemental Cu, or a Cu alloy, such as Cu containing minor amounts of tin (Sn), titanium (Ti), germanium (Ge), zinc (Zn) or magnesium (Mg).